Computer system memory architectures are typically arranged with word bit widths that are a power of two (such as thirty-two and sixty-four) which provide for easy translation of linear byte addresses to word addresses by simple binary shift operations. Presently, thirty-two bit wide architectures are commonly provided by four "by eight" dynamic random access memories (DRAMs) or two "by sixteen" DRAMs. As computer system applications become more demanding, computer memory system sizes have grown. In expanding a 32-bit wide memory system, typical prior art approaches have required a jump to 64-bits or an increase in address width. In both cases the minimum expanded size is typically twice the baseline 32-bit memory size. For many applications the baseline 32-bit memory size may be too small, but twice the memory baseline is more than needed, resulting in unnecessary cost in a system.
It is possible to implement memory sizes having widths that are not a power of two. For example, a 32-bit wide memory can be increased by a factor of 1.5 by employing six "by eight" or three "by sixteen" DRAMs to provide a 48-bit wide architecture. While such an approach increases memory size without having to double memory size, such architectures are typically avoided, due to the difficulty of implementation, and of providing acceptable performance.
Referring now to FIG. 1, a 48-bit wide memory array 1 is illustrated. The memory 1 consists of a series of 48-bit wide addressable locations 2, each corresponding to a particular word address (shown as 0-6 in the figure). The memory 1 is "packed", with each addressable location 2 being entirely filled by byte addressable data. The byte addressable data are represented by the symbol Bn, where n is a hexadecimal number. The inherent drawback of the memory arrangement in FIG. 1 is that the translation from a linear byte address to the word address used to access individual memory devices requires a divide-by-three operation. For example, to access byte Bn would require generating memory address n/6, which is the equivalent to a binary shift and divide by three. Such an operation is difficult to implement, and adds unwanted delay and complexity, whether implemented in software or hardware. Therefore, 48-bit wide architectures have typically been avoided.
Commonly-owned, U.S. Pat. No. 5,598,526 entitled METHOD AND SYSTEM FOR DISPLAYING IMAGES USING DYNAMICALLY RECONFIGURABLE DISPLAY MEMORY ARCHITECTURE and issued to Andrew D. Daniel et al, on Jan. 28,1997 incorporated by reference herein, discloses a memory system having a 48-bit wide architecture wherein 8-bit, 16-bit and 24-bit pixel regions share the same memory. The memory system makes a 48-bit wide memory array usable for 24-bit RGB pixel data, while at the same time, being reconfigurable to 32-bit or 64-bit pixel depths. A drawback to the system disclosed in Daniel et al. is that in reconfiguring the 48-bit wide system for use with non-24-bit pixel data, one third of available RAM storage is lost.